1. Field of the Invention
The present invention relates to a transfer scheme of video data and, particularly, to a transfer scheme that reduces the processing load of memory access to store video data.
2. Description of Related Art
In a real-time video processing system, it is necessary not only to simply transmit and receive a video but also to perform manipulation of a video, such as combining a plurality of images, in order to realize various services. In the manipulation of a video, it is necessary to decode encoded video data once and perform processing on non-compressed image data. There are various kinds of manipulation processing depending on users to receive services, and they should be flexibly variable. For this reason, it is difficult to process image data with use of a common device, and therefore image data is generally manipulated with use of techniques according to services. For example, Japanese Unexamined Patent Application Publications Nos. 2001-103486, 5-191801, 6-334981 and 10-13825 disclose related techniques.
FIG. 11 shows an exemplary configuration of a real-time moving image processing system that decodes encoded video data into non-compressed image data (frame data) once and then performs processing on the frame data. The exemplary system includes decoding units 10-0 to 10-P (P is an integer satisfying P>0), frame processing units 11-0 to 11-Q (Q is an integer satisfying Q>0), and frame memories 12-0 to 12-P. A region where the plurality of frame memories 12-0 to 12-P are placed is a shared memory space 13. The number of decoding units and frame memories (P+1) is determined according to the number of input moving image data. The number of frame processing units (Q+1) is determined according to the number of kinds of manipulating frame data.
The decoding units 10-0 to 10-P perform decoding on a plurality of input moving image data 0 to P and output frame data (framed data) to the shared memory space 13. At this time, the decoding units 10-0 to 10-P output the frame data to a previously associated one of the frame memories 12-0 to 12-P included in the shared memory space 13.
The frame memories 12-0 to 12-P store the frame data that are generated by decoding the input moving image data 0 to P in the decoding units 10-0 to 10-P.
The frame processing units 11-0 to 11-Q select and refer to a given frame memory of the frame memories 12-0 to 12-P in the shared memory space 13 and perform frame processing thereon. The “frame processing” is to perform manipulation processing on the decoded frame data according to a service. The processing includes re-encoding such as image composition or image size change, for example.
In the system shown in FIG. 11, the frame memories 12-0 to 12-P are used both by the decoding units 10-0 to 10-P and the frame processing units 11-0 to 11-Q. Specifically, the decoding units 10-0 to 10-P write the frame data into the corresponding frame memories 12-0 to 12-P in the shared memory space 13. On the other hand, the frame processing units 11-0 to 11-Q read the frame data stored in the frame memories 12-0 to 12-P. Therefore, the frame memories 12-0 to 12-P need to exist in the shared memory space 13 that is accessible by both units.
Consider, for example, the case of broadcasting one input moving image data in a system that performs different frame processing on frame data according to users to receive distribution, regarding the system configuration shown in FIG. 11. A specific example is broadcasting moving image data of a videoconference to every user.
In this case, the frame processing units 11-0 to 11-Q distribute the input moving image data 0, for example, after performing manipulation according to each user. Specifically, the input moving image data 0 is decoded by the decoding unit 10-0 and output to the frame memory 12-0. Then, all the frame processing units 11-0 to 11-Q refer to the frame data stored in the frame memory 12-0. Likewise, the other input moving image data 1 to P are decoded by the decoding units 10-1 to 10-P and output. Then, the frame processing units 11-0 to 11-Q refer to the frame memories 12-1 to 12-P.
In the system as shown in FIG. 11, the decoding units 10-0 to 10-P output the decoded frame data to the frame memories 12-0 to 12-P. On the other hand, the frame processing units 11-0 to 11-Q refer to the frame memories 12-0 to 12-P included in the shared memory space 13. Therefore, access competition to the frame memories 12-0 to 12-P occurs between the decoding units 10-0 to 10-P and the frame processing units 11-0 to 11-Q. Thus, when either one of the decoding units 10-0 to 10-P or the frame processing units 11-0 to 11-Q access the frame memories 12-0 to 12-P, the other units are in a wait state, causing a delay in processing.
Further, in the case where the frame processing units 11-0 to 11-Q operate independently of one another, the plurality of frame processing units 11-0 to 11-Q simultaneously refer to the same frame memory 12-0 to 12-P in some cases, which causes a wait for acquiring the frame data stored in the frame memory 12-0 to 12-P. Therefore, access competition to the frame memory 12-0 to 12-P occurs between the plurality of frame processing units 11-0 to 11-Q. This affects the performance of frame processing.
As described above, there is an issue that processing load occurs due to access competition to the frame memories 12-0 to 12-P in the shared memory space 13.